? 2002 fairchild semiconductor corporation ds005971 www.fairchildsemi.com october 1987 revised april 2002 cd4049ubc ? cd4050bc hex inverting buffer hex non-inverting buffer cd4049ubc cd4050bc hex inverting buffer hex non-inverting buffer general description the cd4049ubc and cd4050bc hex buffers are mono- lithic complementary mos (cmos) integrated circuits con- structed with n- and p-channel enhancement mode transistors. these devices feature logic level conversion using only one supply voltage (v dd ). the input signal high level (v ih ) can exceed the v dd supply voltage when these devices are used for logic level conversions. these devices are intended for use as hex buffers, cmos to dtl/ ttl converters, or as cmos current drivers, and at v dd = 5.0v, they can drive directly two dtl/ttl loads over the full operating temperature range. features wide supply voltage range: 3.0v to 15v direct drive to 2 ttl loads at 5.0v over full temperature range high source and sink current capability special input protection permits input voltages greater than v dd applications ? cmos hex inverter/buffer cmos to dtl/ttl hex converter cmos current ?sink? or ?source? driver cmos high-to-low logic level converter ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. connection diagrams pin assignments for dip cd4049ubc top view cd4050bc top view order number package number package description cd4049ubcm m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow cd4049ubcn n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide cd4050bcm m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow cd4050bcn n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 cd4049ubc cd4050bc schematic diagrams cd4049ubc 1 of 6 identical units cd4050bc 1 of 6 identical units
3 www.fairchildsemi.com cd4049ubc cd4050bc absolute maximum ratings (note 1) (note 2) recommended operating conditions (note 2) note 1: ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. the table of ? recom- mended operating conditions ? and ? electrical characteristics ? provides conditions for actual device operation. note 2: v ss = 0v unless otherwise specified. dc electrical characteristics (note 3) note 3: v ss = 0v unless otherwise specified. supply voltage (v dd ) ? 0.5v to + 18v input voltage (v in ) ? 0.5v to + 18v voltage at any output pin (v out ) ? 0.5v to v dd + 0.5v storage temperature range (t s ) ? 65 c to + 150 c power dissipation (p d ) dual-in-line 700 mw small outline 500 mw lead temperature (t l ) (soldering, 10 seconds) 260 c supply voltage (v dd ) 3v to 15v input voltage (v in ) 0v to 15v voltage at any output pin (v out ) 0 to v dd operating temperature range (t a ) cd4049ubc, cd4050bc ? 55 c to + 125 c symbol parameter conditions ? 55 c + 25 c + 125 c units min max min typ max min max i dd quiescent device current v dd = 5v 1.0 0.01 1.0 30 a v dd = 10v 2.0 0.01 2.0 60 v dd = 15v 4.0 0.03 4.0 120 v ol low level output voltage v ih = v dd , v il = 0v, |i o | < 1 a v dd = 5v 0.05 0 0.05 0.05 v v dd = 10v 0.05 0 0.05 0.05 v dd = 15v 0.05 0 0.05 0.05 v oh high level output voltage v ih = v dd , v il = 0v, |i o | < 1 a v dd = 5v 4.95 4.95 5 4.95 v v dd = 10v 9.95 9.95 10 9.95 v dd = 15v 14.95 14.95 15 14.95 v il low level input voltage |i o | < 1 a (cd4050bc only) v dd = 5v, v o = 0.5v 1.5 2.25 1.5 1.5 v v dd = 10v, v o = 1v 3.0 4.5 3.0 3.0 v dd = 15v, v o = 1.5v 4.0 6.75 4.0 4.0 v il low level input voltage |i o | < 1 a (cd4049ubc only) v dd = 5v, v o = 4.5v 1.0 1.5 1.0 1.0 v v dd = 10v, v o = 9v 2.0 2.5 2.0 2.0 v dd = 15v, v o = 13.5v 3.0 3.5 3.0 3.0 v ih high level input voltage |i o | < 1 a (cd4050bc only) v dd = 5v, v o = 4.5v 3.5 3.5 2.75 3.5 v v dd = 10v, v o = 9v 7.0 7.0 5.5 7.0 v dd = 15v, v o = 13.5v 11.0 11.0 8.25 11.0 v ih high level input voltage |i o | < 1 a (cd4049ubc only) v dd = 5v, v o = 0.5v 4.0 4.0 3.5 4.0 v v dd = 10v, v o = 1v 8.0 8.0 7.5 8.0 v dd = 15v, v o = 1.5v 12.0 12.0 11.5 12.0 i ol low level output current v ih = v dd , v il = 0v (note 4) v dd = 5v, v o = 0.4v 5.6 4.6 5 3.2 ma v dd = 10v, v o = 0.5v 12 9.8 12 6.8 v dd = 15v, v o = 1.5v 35 29 40 20 i oh high level output current v ih = v dd , v il = 0v (note 4) v dd = 5v, v o = 4.6v ? 1.3 ? 1.1 ? 1.6 ? 0.72 ma v dd = 10v, v o = 9.5v ? 2.6 ? 2.2 ? 3.6 ? 1.5 v dd = 15v, v o = 13.5v ? 8.0 ? 7.2 ? 12 ? 5 i in input current v dd = 15v, v in = 0v ? 0.1 ? 10 ? 5 ? 0.1 ? 1.0 a v dd = 15v, v in = 15v 0.1 10 ? 5 0.1 1.0
www.fairchildsemi.com 4 cd4049ubc cd4050bc dc electrical characteristics (continued) note 4: these are peak output current capabilities. continuous output current is rated at 12 ma maximum. the output current should not be allowed to exceed this value for extended periods of time. i ol and i oh are tested one output at a time. ac electrical characteristics (note 5) cd4049ubc t a = 25 c, c l = 50 pf, r l = 200k, t r = t f = 20 ns, unless otherwise specified note 5: ac parameters are guaranteed by dc correlated testing. ac electrical characteristics (note 6) cd4050bc t a = 25 c, c l = 50 pf, r l = 200k, t r = t f = 20 ns, unless otherwise specified note 6: ac parameters are guaranteed by dc correlated testing. symbol parameter conditions min typ max units t phl propagation delay time v dd = 5v 30 65 ns high-to-low level v dd = 10v 20 40 v dd = 15v 15 30 t plh propagation delay time v dd = 5v 45 85 ns low-to-high level v dd = 10v 25 45 v dd = 15v 20 35 t thl transition time v dd = 5v 30 60 ns high-to-low level v dd = 10v 20 40 v dd = 15v 15 30 t tlh transition time v dd = 5v 60 120 ns low-to-high level v dd = 10v 30 55 v dd = 15v 25 45 c in input capacitance any input 15 22.5 pf symbol parameter conditions min typ max units t phl propagation delay time v dd = 5v 60 110 ns high-to-low level v dd = 10v 25 55 v dd = 15v 20 30 t plh propagation delay time v dd = 5v 60 120 ns low-to-high level v dd = 10v 30 55 v dd = 15v 25 45 t thl transition time v dd = 5v 30 60 ns high-to-low level v dd = 10v 20 40 v dd = 15v 15 30 t tlh transition time v dd = 5v 60 120 ns low-to-high level v dd = 10v 30 55 v dd = 15v 25 45 c in input capacitance any input 5 7.5 pf
5 www.fairchildsemi.com cd4049ubc cd4050bc switching time waveforms typical applications cmos to tll or cmos at a lower v dd v dd1 v dd2 in the case of the cd4049ubc the output drive capability increases with increasing input voltage. e.g., if v dd1 = 10v the cd4049ubc could drive 4 ttl loads.
www.fairchildsemi.com 6 cd4049ubc cd4050bc physical dimensions inches (millimeters) unless otherwise noted 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m16a
7 www.fairchildsemi.com cd4049ubc cd4050bc hex inverting buffer hex non-inverting buffer physical dimensions inches (millimeters) unless otherwise noted (continued) 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n16e fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
careers | sitema go datasheets, samples, buy technical information applications design center support company investors my f a home >> find products >> product status/pricing/packaging cd4049ubc hex inverting buffer general description back to top features back to top contents ? general description ? features ? product status/pricing/packaging ? order samples ? qualification support the cd4049ubc and cd4050bc hex buffers are monolithic complementary mos (cmos) integrated circuits constructed with n- and p-channel enhancement mode transistors. these devices feature logic level conversion using only one supply voltage (v dd ). the input signal high level (v ih ) can exceed the v dd supply voltage when these devices are used for logic level conversions. these devices are intended for use as hex buffers, cmos to dtl/ttl converters, or as cmos current drivers, and at v dd = 5.0v, they can drive directly two dtl/ttl loads over the full operating temperature range. z wide supply voltage range: 3.0v to 15v z direct drive to 2 ttl loads at 5.0v over full temperature range z high source and sink current capability z special input protection permits input voltages greater than v dd datasheet download this datasheet e - mail this datasheet this page print version product product status pb-free status pricing* package type leads packing method package marking convention** related links request samples how to order products product change notices (pcns) support sales support quality and reliability design cente r pa g e 1 of 3 product folder - fairchild p/n cd4049ubc - hex invertin g buffe r 16-au g -2007 mhtml:file://c:\temp\CD4049UBCSJ.mht
back to top qualification support click on a product for detailed qualification data cd4049ubcm full production $0.172 soic 16 rail line 1: $y (fairchild logo) & z (asm. plant code) & 2 (2-digit date code) & t (die trace code) line 2: cd4049ubcm cd4049ubcmx full production $0.172 soic 16 tape reel line 1: $y (fairchild logo) & z (asm. plant code) & 2 (2-digit date code) & t (die trace code) line 2: cd4049ubcm cd4049ubcn full production $0.265 dip 16 rail line 1: $y (fairchild logo) & z (asm. plant code) & 4 (4-digit date code) & t (die trace code) & p (marketing status code) line 2: cd4049ubcn CD4049UBCSJ full production $0.233 sop 16 rail line 1: $y (fairchild logo) & z (asm. plant code) & 2 (2-digit date code) & t (die trace code) line 2: cd4049ubc CD4049UBCSJx full production $0.233 sop 16 tape reel line 1: $y (fairchild logo) & z (asm. plant code) & 2 (2-digit date code) & t (die trace code) line 2: cd4049ubc * fairchild 1,000 piece budgetary pricing ** a sample button will appear if the part is available through fa irchild's on-line samples program. if there is no sample butt on, please contact a fairchild distributo r to obtain samples indicates product with pb -free second-level interconne ct. for more information click here. package marking information for product cd4049ubc is available. click here for more information . product cd4049ubcm cd4049ubcmx cd4049ubcn pa g e 2 of 3 product folder - fairchild p/n cd4049ubc - hex invertin g buffe r 16-au g -2007 mhtml:file://c:\temp\CD4049UBCSJ.mht
back to top CD4049UBCSJ CD4049UBCSJx ? 2007 fairchild semiconductor products | design center | support | company news | investors | my fairchild | contact us | site index | privacy policy | site terms & conditions | standard terms & conditions o pa g e 3 of 3 product folder - fairchild p/n cd4049ubc - hex invertin g buffe r 16-au g -2007 mhtml:file://c:\temp\CD4049UBCSJ.mht
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